library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity MULTIPLY_8x8_unsigned is port(
	DINA : in  std_logic_vector(7 downto 0);
	DINB : in  std_logic_vector(7 downto 0);
	DOUT : out std_logic_vector(15 downto 0));
end MULTIPLY_8x8_unsigned;

architecture RTL of MULTIPLY_8x8_unsigned is

component MULTIPLY_2x8 is port(
	DINA : in  std_logic_vector(1 downto 0);
	DINB : in  std_logic_vector(7 downto 0);
	DOUT : out std_logic_vector(9 downto 0));
end component;

signal reslt0 : std_logic_vector(9 downto 0);
signal reslt2 : std_logic_vector(9 downto 0);
signal reslt4 : std_logic_vector(9 downto 0);
signal reslt6 : std_logic_vector(9 downto 0);

begin

MUL0_inst : MULTIPLY_2x8 port map(
	DINA => DINA(1 downto 0),
	DINB => DINB,
	DOUT => reslt0);

MUL2_inst : MULTIPLY_2x8 port map(
	DINA => DINA(3 downto 2),
	DINB => DINB,
	DOUT => reslt2);

MUL4_inst : MULTIPLY_2x8 port map(
	DINA => DINA(5 downto 4),
	DINB => DINB,
	DOUT => reslt4);

MUL6_inst : MULTIPLY_2x8 port map(
	DINA => DINA(7 downto 6),
	DINB => DINB,
	DOUT => reslt6);

DOUT <= ("000000" & reslt0) + ("0000" & reslt2 & "00") + ("00" & reslt4 & "0000") + (reslt6 & "000000");
end RTL;